1. Technical Field
The present invention relates to a novel low thermal-expansion multilayer circuit board suitable for the mounting of semiconductor devices, a method of manufacturing the same, a substrate for multilayer circuits, and an electronic apparatus.
2. Background Art
In recent years, semiconductor chips are often mounted directly on circuit boards by the so-called bear chip mounting technique, whereby mounting takes place directly without the use of leaded package. However, because the coefficient of thermal expansion of semiconductor devices differs from that of circuit boards, cracks or peeling can occur in the solder-connected portions linking semiconductor devices and circuit boards. This occurs due to temperature changes that result when the electronic equipment on which a circuit board is mounted is activated, leading to faulty electrical connections. In order to bring the coefficient of thermal expansion of the circuit board closer to that of the semiconductor devices, a metal-core substrate has been adopted in which a plate of an alloy with a small coefficient of thermal expansion is laid.
Iron-nickel alloys with a nickel content of about 36–42 mass % are often used for the alloy plate. This is because their coefficient of thermal expansion is about 1–5×10−6/° C., which is on the same order as the coefficient of thermal expansion of silicon in the semiconductor devices, which is about 3×10−6/° C. While the iron-nickel alloy forming the core is electrically insulated from the circuit in a typical metal-core substrate, it is sometimes used as a power supply or ground circuit. However, the iron-nickel alloys are not suitable for use in circuits because their electric conductivity is low.
JP Patent Publication (Unexamined Application) No. 6-85414 discloses the use of a composite member comprising an iron-nickel alloy coated by copper on either side in a printed circuit board. The publication, however, does not describe layer-to-layer interconnection.
JP Patent Publication (Unexamined Application) No. 11-354684 discloses the formation of a composite member in which an iron-nickel alloy coated with copper on one side is stacked via a polyimide-resin insulating layer. While the publication also describes through-hole via-holes, the layer-to-layer interconnection is carried out by soldering.
JP Patent Publication (Unexamined Application) Nos. 5-251868, 9-162550, 11-261236, and 2001-342574 each disclose multilayer circuit boards having blind via-holes communicated to the wiring layer, where a circuit pattern is formed in the non-through holes.
None of the publications, however, disclose the formation of layer-to-layer interconnections in a low expansion multilayer wiring board comprising an iron-nickel alloy composite member formed with copper plating. Further, the publication in which a circuit pattern is formed in blind via-holes does not disclose a low expansion wiring board. While JP Publication (Unexamined Application) No. 2001-342574 discloses the example of an iron-nickel alloy in the core substrate, it does not describe the wiring of the iron-nickel alloy and its layer-to-layer interconnection.
JP Patent Publication (Unexamined Application) No. 11-354684 does not disclose the formation of outer-layer wiring on the insulator surface by plating.